Compound Semiconductor Materials

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Compound semiconductor is a type of semiconductor material composed of compounds. Compared with the widely used semiconductor material Si, wide band gap (WBG) compound semiconductors have superior material characteristics such as high voltage resistance, high current resistance, high heat dissipation efficiency, and high operating frequency, which have gradually attracted attention. Representative WBG materials are silicon carbide (SiC) and gallium nitride (GaN), which have the advantages of improving energy efficiency and reducing conversion loss in power electronics and 5G high-frequency applications.

We provide the following products:

SiC Crystal Grower (HTCVD/PVT)

Due to the specification of high temperature and stable, Single Silicon Carbide are usually used for semiconductor field. Nowadays, High-Temperature Chemical Vapor Deposition(HTCVD) and Physical Vapor Transport(PVT) are common in the SiC crystal growing method. These two method are available for mass production.

SiCube is used with HTCVD and PVT method for mass production.

Technical Data

1. Diameter：4 inch

2. Pressure : 5 – 900 mbar

3. Temperature : 2600 °C

4. Electric Power : 80kw

5. Electric Frequency : 6~8 kHz

6. Size : 2000 x 2500 x 3725 mm

7. Weight(total) : 3800kg

baSiC-T is used to mass production for 4-6 inch diameter crystal with HTCVD method.

Technical Data

1. Diameter：4 ~6 inch

2. Pressure : 1 – 900 mbar

3. Temperature : 2600 °C

4. Electric Power : 60 kw

5. Electric Frequency : 6~12 kHz

6. Size : 2000 x1200 x 2800 mm

7. Weight(total) : Approx. 2000kg

Video Reference:

* Please contact us for more product details.

Substrate

SiC wafer (substrate)

Silicon carbide (SiC), also known as carborundum, is a compound of silicon and carbon with chemical formula SiC.SiC is a Ⅳ-Ⅳ compound semiconductor material, with a variety Allotropic. The typical structure of which is divided into two types, first type is sphalerite crystal structure as 3C-SiC (β-SiC),second type is wurtzite hexagonal crystal structure; typically a 6H-SiC, 4H-SiC and 15R-SiC known as α-SiC. The most commonly used in the semiconductor industry are 4H-SiC and 6H-SiC structures.

There are some advantages for SiC:
–Current density can easily reach 5 or even 10 A/mm² (less than 1 A/mm² for silicon)
–Breakdown voltage (Volt/μm of epilayer) is typically in the 100 V/μm range for SiC, compared to 10 V/μm for silicon
–A single SiC device will drive higher current and voltage in a reduced foot-print.
–SiC is intrinsically very thermally conductive. Where a Silicon device will have to be cooled down to not exceed 85 °C, a similar SiC device will operate at 250°C with no degradation. This robustness to higher operation temperature will allow cost savings at system or module level where the cooling features (air, water, fans, heat sinks…) will be considerably reduced and shrunk.

•Higher electron mobility of SiC also permits higher frequency operation in switching mode.

Latentek can provide high quality single crystalline Silicon carbide wafer; furthermore, we provide two forms of wafer: semi-insulating and conductive as to meet the customer needs of high-frequency components and high power components. Current technical ability is able to provide MPD< 1 specifications of the wafer.

SiC Wafer Specification

4-inch Specifications of 4H-SiC High-Purity Semi-Insulating Substrate

Property	Production grade	Research grade	Dummy grade
Diameter	100.0mm+0.0/-0.5mm
Surface Orientation	{0001}±0.2°
Primary Flat Orientation	<11-20>±5.0°
Secondary Flat Orientation	90.0° CW from Primary Flat ±5.0°, Si Face up
Primary Flat Length	32.5mm±2.0mm
Secondary Flat Length	18.0mm±2.0mm
Wafer Edge	Chamfer
Micro Pipe Density	≦5micropipes/cm ²	≦10micropipes/cm ²	≦50micropipes/cm ²
Polytype Area by High-intensity Light	None		≦10% of Whole Area
Resistivity	≧ 1E7Ω‧cm		(Area75%) ≧ 1E7Ω‧cm
Thickness	500.μm±25.μm or 350.0μm±25.μm
TTV	≦10μm		≦15μm
Bow (Absolute Value)	≦25μm		≦30μm
Warp	≦45μm
Surface Roughness	Si-Face CMP Ra ≦0.5nm		N/A
Cracks by High-intensity Light	None
Edge Chips/Indents by Diffuse Lighting	none	Qty. ≦2, the length and width of each<1.0mm

4-inch Specifications of 4H-SiC N-type Substrate

Product performance	U level	P grade	R grade	Class D
diameter	100.0mm+0.0/-0.5mm
Surface orientation	Crystal orientation: 4°, <11-20>±0.5°
Primary reference plane orientation	<11-20>±5.0°
Secondary reference plane orientation	Clockwise 90°±5.0° with the main reference surface, Si face up
Length of main reference surface	32.5mm±2.0mm
Length of secondary reference surface	18.0mm±2.0mm
Chip edge	Chamfer
Microtubule density	≦1pcs/cm ²	≦5pcs/cm ²	≦10pcs/cm ²	≦50pcs/cm ²
Polytype	Not allowed			Cumulative area≦10%
Resistivity	0.015Ω ‧ cm～0.028Ω ‧ cm			(75% area) 0.015Ω‧cm ~0.028Ω ‧ cm
thickness	350.0μm±25.0μm or 500.0μm±25.0μm
Total thickness change	≦10μm			≦15μm
Deflection value (absolute value)	≦25μm			≦30μm
Warpage	≦45μm
Surface treatment	C-side: optical polishing; Si-side: chemical mechanical polishing (CMP)
Surface roughness	Si-surface CMP Ra≦0.5nm			N/A
Crack (observed by strong light)	Not allowed
Edge collapse/notch (observation of diffuse reflection light)	Not allowed		≦2, and each length and width are <1.0mm

6-inch Specifications of 4H-SiC N-type Substrate

Product performance	standard
diameter	150.0mm±0.25mm
Surface orientation	Crystal orientation: 4°, <11-20>±0.5°
Primary reference plane orientation	<11-20>±5.0°
Secondary reference plane orientation	N/A
Length of main reference surface	47.5mm±2.0mm
Length of secondary reference surface	N/A
Chip edge	Chamfer
Microtubule density	≦5pcs/cm ²
Polytype	Not allowed
Resistivity	0.015Ω ‧ cm～0.028Ω ‧ cm
thickness	350.0μm±25.0μm
Total thickness change	≦10μm
Deflection value (absolute value)	≦40μm
Warpage	≦60μm
Surface treatment	Double-sided polishing; Si surface CMP
Crack (observed by strong light)	Not allowed
Edge collapse/notch (observation of diffuse reflection light)	Not allowed

(2) Physical display of silicon carbide wafers

* If there are other specifications needs, please contact us to discuss.

GaN

GaN Substrates

2 inch GaN Template

Product number	GaN-TCU-C50	GaN-TCN-C50	GaN-TCP-C50
size	Ф50.8 ± 0.1 mm	Ф50.8 ± 0.1 mm	Ф50.8 ± 0.1 mm
thickness	4.5±0.5 µm, 20±2 µm	4.5±0.5 µm, 20±2 µm	4.5±0.5 µm
Crystal orientation	C-plane(0001) ± 0.5°	C-plane(0001) ± 0.5°	C-plane(0001) ± 0.5°
Conductivity type	N-type(Undoped)	N-type(Si-doped)	P-type(Mg-doped)
Resistivity (300 K)	<0.5Ω·cm	<0.05Ω·cm	~10Ω·cm
Carrier concentration	<5×10 ¹⁷ cm ^-3	> 1×10 ¹⁸ cm ^-3	> 6×10 ¹⁶ cm ^-3
Mobility	~ 300cm ² /V•s	~ 200cm ² /V•s	~ 10cm ² /V•s
Dislocation density	Less than 5×10 ⁸ cm ^-2 (estimated by FWHMs of XRD)	Less than 5×10 ⁸ cm ^-2 (estimated by FWHMs of XRD)	Less than 5×10 ⁸ cm ^-2 (estimated by FWHMs of XRD)
Substrate structure	GaN on sapphire (standard :SSP option:DSP)	GaN on sapphire (standard :SSP option:DSP)	GaN on sapphire (standard :SSP option:DSP)
Effective area	>90%	>90%	>90%
package	Packaged in a class 100 clean room environment, in cassette of 25pcs	Packaged in a class 100 clean room environment, in cassette of 25pcs	Packaged in a class 100 clean room environment, in cassette of 25pcs
package	or single container, under a nitrogen atmosphere.	or single container, under a nitrogen atmosphere.	or single container, under a nitrogen atmosphere.

2 inch Free-Standing GaN Substrate

Product number	GaN-FS-CU-C50	GaN-FS-CN-C50	GaN-FS-C-SI-C50
size	Ф 50.8 ± 1 mm	Ф 50.8 ± 1 mm	Ф 50.8 ± 1 mm
thickness	350 ± 30 µm	400 ± 30 µm	350 ± 30 µm
Effective area	>90%	>90%	>90%
Crystal orientation	C-plane (0001) off angle toward M-Axis 0.35°± 0.15°	C-plane (0001) off angle toward M-Axis 0.35°± 0.15°	C-plane (0001) off angle toward M-Axis 0.35°± 0.15°
Main positioning edge	(1-100)±0.5°, 16.0±1.0mm	(1-100)±0.5°, 16.0±1.0mm	(1-100)±0.5°, 16.0±1.0mm
Secondary positioning edge	(11-20)±3°,8.0±1.0mm	(11-20)±3°,8.0±1.0mm	(11-20)±3°,8.0±1.0mm
TTV	≤ 15µm	≤ 15µm	≤ 15µm
Curvature	≤ 20µm	≤ 20µm	≤ 20µm
Conductivity type	N-type	N-type	Semi-Insulating
Resistivity (300 K)	<0.5Ω·cm	<0.05Ω·cm	> 10 ⁶ Ω·cm
Dislocation density	From 1×10 ⁵ to 3×10 ⁶ cm ^-2	From1x10⁵ to3x10⁶ cm^-2	From1x10⁵ to 3×10⁶ cm^-2
Polishing	Front surface：Ra＜0.2 nm(polished);	Front surface：Ra＜0.2 nm(polished);	Front surface：Ra＜0.2 nm(polished);
	or<0.3nm (polished and surface treatment for epitaxy)	or<0.3nm (polished and surface treatment for epitaxy)	or<0.3nm (polished and surface treatment for epitaxy)
	Back Surface：0.5~1.5μm;	Back Surface：0.5~1.5μm;	Back Surface：0.5~1.5μm;
	option：1-3nm (Fine ground); < 0.2nm(polished)	option：1-3nm (Fine ground); < 0.2nm(polished)	option：1-3nm (Fine ground); < 0.2nm(polished)
package	Packaged in a class 100 clean room environment,	Packaged in a class 100 clean room environment,	Packaged in a class 100 clean room environment,
package	in single container,under a nitrogen atmosphere.	in single container,under a nitrogen atmosphere.	in single container,under a nitrogen atmosphere.

10×10.5mm² Free-Standing GaN Substrate

Product number	GaN-FS-C-U-S10	GaN-FS-C-N-S10	GaN-FS-C-SI-S10
Dimensions	10×10.5mm²	10×10.5mm²	10×10.5mm²
Thickness	350±30μm	400±30μm	350±30μm
Orientation	C-plane（0001）off angle toward M-Axis 0.35°±0.15°	C-plane（0001）off angle toward M-Axis 0.35°±0.15°	C-plane（0001）off angle toward M-Axis 0.35°±0.15°
TTV	≤10µm	≤10µm	≤10µm
BOW	≤10µm	≤10µm	≤10µm
Conduction Type	N-type	N-type	Semi-Insulating
Resistivity（300 K）	< 0.5Ω·cm	< 0.05Ω·cm	> 10⁶Ω·cm
Dislocation Density	From 1×10⁵ to 3×10⁶cm^-2	From 1×10⁵ to 3×10⁶cm^-2	From 1×10⁵to 3×10⁶cm^-2
Useable Surface Area	>90%	>90%	>90%
Polishing	Front Surface：Ra＜0.2 nm(polished);	Front Surface：Ra＜0.2 nm(polished);	Front Surface：Ra＜0.2 nm(polished);
	or <0.3nm(polished and surface treatment for epitaxy)	or <0.3nm(polished and surface treatment for epitaxy)	or <0.3nm(polished and surface treatment for epitaxy)
	Back Surface：0.5~1.5μm;	Back Surface：0.5~1.5μm;	Back Surface：0.5~1.5μm;
	option：1-3nm(Fine ground);<0.2nm(polished)	option：1-3nm(Fine ground);<0.2nm(polished)	option：1-3nm(Fine ground)；<0.2nm(polished)
Package	Packaged in a class 100 clean room environment,	Packaged in a class 100 clean room environment,	Packaged in a class 100 clean room environment,
Package	in single container,under a nitrogen atmosphere.	in single container,under a nitrogen atmosphere.	iin single container,under a nitrogen atmosphere.

Non-Polar and Semi-Polar Free-Standing GaN Substrate

Product number	GaN-FS-A-U/N/SI-S	GaN-FS-M-U/N/SI-S	GaN-FS-SP-U/N/SI-S
Dimensions	（5.0~10.0）× 10.0 mm²	（5.0~10.0）× 10.0 mm²	（5.0~10.0）× 10.0 mm²
Dimensions	（5.0~10.0）× 20.0mm²	（5.0~10.0）× 20.0mm²	（5.0~10.0）× 20.0mm²
Thickness	350±25μm	350±25μm	350±25μm
Plane	(11-20)	(1-100)	(20-21) (20-2-1) (11-22) (10-11)
Miscut Angle	-1°±0.2°	-1°±0.2°	-1°±0.2°
TTV	≤10µm	≤10µm	≤10µm
BOW	≤10µm	≤10µm	≤10µm
Conduction Type	N-type < 0.1Ω·cm	N-type < 0.1Ω·cm	N-type < 0.1Ω·cm
Resistivity（300 K）	N-type < 0.05Ω·cm	N-type < 0.05Ω·cm	N-type < 0.05Ω·cm
	Semi-Insulating > 10⁶Ω·cm	Semi-Insulating > 10⁶Ω·cm	Semi-Insulating > 10⁶Ω·cm
Dislocation Density	From 1×10⁵ to 3×10⁶cm^-2	From 1×10⁵ to 3×10⁶ cm^-2	From 1×10⁵ to 3×10⁶ cm^-2
Useable Surface Area	>90%	>90%	>90%
Polishing	Front Surface：Ra＜0.2 nm（polished）;	Front Surface：Ra＜0.2 nm（polished）	Front Surface：Ra＜0.2 nm（polished）
	Back Surface：1-3nm（fine ground）;	Back Surface：1-3nm(fine ground);	Back Surface：1-3nm（fine ground）;
	option：<0.2nm（polished）	option：<0.2nm(polished).	option：<0.2nm（polished）.
Package	Packaged in a class 100 clean room environment,	Packaged in a class 100 clean room environment,	Packaged in a class 100 clean room environment,
Package	in single container,under a nitrogen atmosphere.	in single container,under a nitrogen atmosphere.	in single container,under a nitrogen atmosphere.

4 inch GaN Template

Product number	GaN-T-C-U-C100	GaN-T-C-N-C100
Dimensions	Ф 100 ± 0.1 mm	Ф 100 ± 0.1 mm
Thickness	4.5±0.5 µm, 20±2 µm	4.5±0.5 µm, 20±2 µm
Orientation	C-plane(0001) ± 0.5°	C-plane(0001) ± 0.5°
Conductivity type	N-type(Undoped)	N-type(Si-doped)
Resistivity (300 K)	<0.5Ω·cm	<0.05Ω·cm
Carrier concentration	<5×10 ¹⁷ cm ^-3	> 1×10 ¹⁸ cm ^-3
Mobility	~ 300cm ² /V•s	~ 200cm ² /V•s
Dislocation density	Less than 5×10 ⁸ cm ^-2 (estimated by FWHMs of XRD)	Less than 5×10 ⁸ cm ^-2 (estimated by FWHMs of XRD)
Substrate structure	GaN on sapphire (standard :SSP option:DSP)	GaN on sapphire (standard :SSP option:DSP)
Effective area	>90%	>90%
Package	Packaged in a class 100 clean room environment, in cassette of 25pcs	Packaged in a class 100 clean room environment, in cassette of 25pcs
Package	or single container, under a nitrogen atmosphere.	or single container, under a nitrogen atmosphere.

AIN

2 inch AlN Template

Product number	AlN-TC-C50
size	Ф 50.8 ± 0.1 mm
thickness	4±1.5µm
Crystal orientation	C-plane (0001)
Conductivity type	Semi-Insulating
Crystal quality	XRD FWHM of (0002) <350 arcsec
Crystal quality	XRD FWHM of (1012) <450 arcsec
Surface roughness	Ra <5 nm (10 x 10 µm ² )
Substrate structure	AlN on sapphire (SSP)
Effective area	Exclusion zone< 2 mm
package	Packaged in a class 100 clean room environment, in cassette of 25pcs
package	or single container, under a nitrogen atmosphere.

SiC epi-wafer

SiC on SiC

SiC Epitaxial Wafer

SiC epitaxial wafer are used in a variety of electronic components such as: Shockley Diodes, MOSFET, JFET, BJT, Thyristor, GTO and IGBT. Please refer to our 4″~6″ SiC specifications or contact us directly.

4H-SiC Epi-Wafer Standard Specification (150mm & 100mm & 76.2mm)

Substrate orientation : Epitaxy is only available for off-axis substrates
Doping
	n-type	p-type
Dopant	Nitrogen	Aluminum
Net Doping Density	N_D-N_A	N_A-N_D
Silicon Face	9E14~1E19cm^-3	9E14~1E19cm^-3
Tolerance	± 15%	± 50%
Uniformity	≦ 10%	≦ 20%
Thickness: 0.2~100µm
Tolerance	± 10%
Uniformity	≦ 5%

Characteristics	Acceptable Limits	Definitions	Test Methods
Epi Defects	2mm*2mm die yield ≥ 95%	Defects only include triangular defects, downfalls, carrots and comets.	candela CS920
Edge Chips	≦ 2 with radius 1.5mm	Areas where material has been unintentionally peeled off from the wafer	High Intensity illumination
Scratches	≦ 10 lines total and the total length of these lines should be less than wafer diameter	Grooves or cuts below the surface plane of the wafer having a length-to-width ratio of greater than 5 to 1
Surface Roughness	<0.5mm	20µm*20µm scanned by AFM
Backside Cleanliness	100% clean	None contamination
Thickness	see specification table	Thickness is determined as an average value across the wafer by FTIR	FTIR
Net doping	see specification table	Net doping is determined as an average value across the wafer by MCV.	MCV

SiC Epi-Wafer thickness Uniformity Distribution Chart

mean value(µm):	12.04
sigma/mean:	1.28%
(max-min)/(max+min):	3.04%

SiC Epi-Wafer Doping Unformity Distribution Chart

mean value(cm^-3):	7.95¹⁵
sigma/mean:	3.48%
(max-min)/(max+min):	9.97%

GaN on SiC

If you have any related requirements, please feel free to contact us, and we will ask someone to evaluate and quote for you.

CVD SiC

CVD SiC Bulk Synthesis

Feature:

• Ultra-pure 99.999% (by GDMS)

• Outstanding corrosion resistance in plasma applications

• Proven durability in high temperature ammonia environments

• Excellent thermal shock resistant

• High thermal conductivity

• Excellent stiffness to weight ratio

• Fine grained microstructure

• Non-porous

SiC bulk material for semi-tool(high-temp., high-erosion environment)

Raw material for SiC crystalline growth

High purity CVD SiC Parts for Semiconductor

High temp., high erosion

Rapid thermal process, etching rings

Plasma etching

MOCVD

High purity CVD SiC Granular for Crystal Growth | Customize Size

Silicon Carbide (Low Nitrogen)

Silicon Carbide (Standard)

Address: 10th Floor, No. 86-3, Yiwen 1st Street, Taoyuan District, Taoyuan City, TAIWAN

TEL: + 886 3-3589738